Design Space Exploration in an FPGA-Based Software Defined Radio

International audienceThe FPGA (Field Programmable Gate Array) technology is expected to play a key role in the development of Software Defined Radio (SDR) platforms. To this aim, leveraging the nascent High-Level Synthesis (HLS) tools, a design flow from high-level specifications to Register-Transfer Level (RTL) description can be thought. Based on such a flow, this paper describes the Design Space Exploration (DSE) that can be achieved using loop optimizations. The mainstream objective is to demonstrate the compile-time flexibility of an architecture when associated with a reconfigurable platform. Throughout both IEEE 802.15.4 and IEEE 802.11g waveform examples, we show how the FPGA resources can be tuned according to a targeted throughput

An FPGA Software Defined Radio Platform with a High-Level Synthesis Design Flow

International audienceSoftware defined radio (SDR) opens a new door to future Internet of Things with higher degree of designing flexibility in context of wireless system development. Prototyping a remote implementation of wireless protocols on a hardware over the web requires a highly versatile software radio platform along with laid-back designing tools. To this aim, an FPGA-based SDR scheme has been proposed combining Virtex-6 Perseus 6010 platform capabilities and a design flow based on High-Level Synthesis (HLS) tools. A full IEEE 802.15.4 (ZigBee) physical layer has been implemented on the proposed platform from a C-language dataflow specification. All the results have been analyzed to lead to a fair comparison between different design flows. Although the proposed SDR has some designing issues, it shows a noticeable designing potentiality to flexible prototyping of future wireless systems

Synthèse automatique d’accélérateurs matériels depuis des spécifications de haut niveau de formes d’ondes pour la radio flexible

The Internet of Things (IoT) aims at connecting billions of communicating devices through an internet-like network. To this aim, the access to these things is expected to be performed via wireless technologies without using any predefined infrastructures or standards. This technology requires defining and implementing smart nodes capable to adapt to different radio communication protocols. In this thesis, we have defined a design methodology/flow, for such smart nodes, starting from their high-level specification down to their implementation in FPGA fabrics. This flow aims at improving the programmability of the waveforms by leveraging some high-level specifications. Thus, it relies on the High-Level Synthesis (HLS) for rapid prototyping of the waveforms functional blocks as well as the dataflow model of computation. Its entry point is Domain-Specific Language which enables modeling a waveform while inserting some implementation constraints for reconfigurable architectures such as the FPGAs. The flow is featured with a compiler which purpose is to produce some synthesis scripts and generate some RTL source code. The final waveform consists of a datapath and a control unit implemented as a Hierarchical Finite State Machine (HFSM).L’internet des objets vise à connecter des milliards d’objets physiques ainsi qu’à les rendre accessibles depuis le monde numérique que représente l’internet d’aujourd’hui. Pour ce faire, l’accès à ces objets sera majoritairement réalisé sans fil et sans utiliser d’infrastructures prédéfinies ou de normes spécifiques. Une telle technologie nécessite de définir et d’implémenter des nœuds radio intelligents capables de s’adapter à différents protocoles physiques de communication. Nos travaux de recherches ont consisté à définir un flot de conception pour ces nœuds intelligents partant de leur modélisation à haut niveau jusqu’à leur implémentation sur des cibles de types FPGA. Ce flot vise à améliorer la programmabilité des formes d’ondes par l’utilisation de spécification de haut niveau exécutables et synthétisables, il repose sur la synthèse de haut niveau (HLS pour High Level Synthesis) pour le prototypage rapide des briques de base ainsi que sur le modèle de calcul de types flot de données des formes d’ondes radio. Le point d’entrée du flot consiste en un langage à usage spécifique (DSL pour Domain Specific Language) qui permet de modéliser à haut niveau une forme d’onde tout en insérant des contraintes d’implémentation pour des architectures reconfigurables telles que les FPGA. Il est associé à un compilateur qui permet de générer du code synthétisable ainsi que des scripts de synthèse. La forme d’onde finale est composée d’un chemin de données et d’une entité de contrôle implémentée sous forme d’une machine d’état hiérarchique

Frame-based Modeling for Automatic Synthesis of FPGA-Software Defined Radio

International audienceSoftware Defined Radio (SDR) is now becoming a ubiquitous concept to describe and implement Physical Layers (PHYs) of wireless systems. Moreover, even though the FPGA is expected to play a key role in SDR, describing a PHY at the Register-Transfer-Level (RTL) requires tremendous efforts. This paper introduces a novel methodology to rapidly implement PHYs for SDR. The work relies upon High-Level Synthesis tools and dataflow modeling in order to infer an efficient RTL control unit for the application. The proposed software-based over-layer partly handles the complexity of programming an FPGA and integrates reconfigurable features. It consists essentially of a Domain-Specific Language (DSL) combined to a DSL-Compiler. An IEEE 802.11a transceiver has been explored via this approach in order to show the flexibility features

Description haut niveau de formes d'ondes pour la radio logicielle sur architectures reconfigurables

National audienceThe work depicted in this paper deals with the outstanding context of Software Defined Radio (SDR) and aims at leveraging the FPGA technology to get to a trade-off between energy consumption and platform flexibility. In this paper, we propose a novel approach combining hardware architecture and high level specification. This approach is comprised of a Domain-Specific Language meant for telecommunication systems waveforms and the High Level Synthesis (HLS) tools. It eases the Design Space Exploration and takes advantage of prior knowlegde of the target waveform. Design integration is performed on an FPGA-based platform. Synthesis results of the IEEE 802.15.4 waveform are given considering different description languages (C, VHDL).Les travaux s'inscrivent dans le contexte radio logicielle et proposent une alternative basée sur FPGA dans le but de tirer profit du compromis entre la consommation d'énergie et la flexibilité offert par cette technologie. Dans cet article, nous proposons un flot de conception innovant, alliant architecture matérielle et langage de description haut niveau. Ce flot comprend un langage de description spécifique aux formes d'ondes pour les systèmes de communication et la synthèse matérielle automatique utilisant des outils de synthèse de haut niveau. Cette démarche vise à faciliter l'exploration de l'espace d'architectures tout en bénéficiant de connaissances a priori des formes d'ondes cibles. La description haut niveau est validée sur une plateforme FPGA. Des résultats de synthèse d'une forme d'onde IEEE 802.15.4 sont donnés pour différents langages de description (C, VHDL)

Vers un language spécialisé pour la radio logicielle sur FPGA

National audienceCes travaux s'inscrivent dans le contexte de la radio logicielle et proposent une alternative basée sur la technologie FPGA offrant un bon compromis entre la consommation d'énergie et la flexibilité. Nous proposons ainsi un flot de conception innovant, alliant architecture matérielle et langage de description haut-niveau. Ce flot comprend un langage de description spécifique des formes d'ondes pour les systèmes de communication et la synthèse matérielle automatique utilisant des outils de synthèse de haut-niveau. La description haut-niveau est valid'ee sur une plateforme FPGA. Des résultats de synthèse d'une forme d'onde IEEE 802.15.4 sont donnés pour différents langages de description (C, VHDL)

A Frame-Based Domain-Specific Language for Rapid Prototyping of FPGA-Based Software Defined Radios

International audienceThe field-programmable gate array (FPGA) technology is expected to play a key role in the development of software-defined radio (SDR) platforms. As this technology evolves, low-level designing methods for prototyping FPGA-based applications did not change throughout the decades. In the outstanding context of SDR, it is important to rapidly implement new waveforms to fulfill such a stringent flexibility paradigm. At the current time, different proposals have defined, through softwarebased approaches, some efficient methods to prototype SDR waveforms in a processor-based running environment. This paper describes a novel design flow for FPGA-based SDR applications. This flow relies upon high-level synthesis (HLS) principles and leverages the nascent HLS tools. Its entry point is a domain-specific language (DSL) which handles the complexity of programming an FPGA and integrates some SDR features so as to enable automatic waveform control generation from a data frame model. Two waveforms (IEEE 802.15.4 and IEEE 802.11a) have been designed and explored via this new methodology, and the results are highlighted in this paper

Rapid Prototyping for Video Coding over Flexible Radio Links

International audienc